~ruther/verilog-riscv-semestral-project

ref: 66fd5da9a15539865c07f3516a5e396674a2bf16 verilog-riscv-semestral-project/src d---------
fix: shift by 5 bits in alu
fix: do not set subtract for non-R instructions
fix: make immediates sign extended
fix: remove duplicit instruction and pc in cpu
fix: force alu operation to addition for storing memory and pc
fix: do not use immediate in alu src for SB
fix: propagate conditional jump from control_unit
refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.
refactor: change program mem to file prog mem
fix(register_file): output register if addr not zero
feat: add cpu top level entity
feat: add control_unit wrapper over instruction_decoder
chore: add cpu types for various sources

Better orientation by name instead of
number
feat: add program counter
feat: add program memory
fix: alu arithmetical shift

Has to have signed as arguments
feat(decoder): implement memory mask, conditional jumps
refactor: parametrize register file
chore: move default case
fix: make rd1, rd2 in register_file regs
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