~ruther/verilog-riscv-semestral-project: fix(register_file): output register if addr not zero

0e23dce51761469332c4b654818475721e29d171 — Rutherther 1 year, 5 months ago 82d9e44

fix(register_file): output register if addr not zero

patch browse .tar.gz

1 files changed, 2 insertions(+), 2 deletions(-)

M src/register_file.sv

M src/register_file.sv => src/register_file.sv +2 -2

@@ 19,14 19,14 @@ module register_file(clk, a1, a2, a3, we3, wd3, rd1, rd2);
   wire          clk;
 
   always_comb begin
-    if (a1 == {ADDRESS_LENGTH{1'b0}})
+    if (a1 != {ADDRESS_LENGTH{1'b0}})
       rd1 = gprs[a1];
     else
       rd1 = 32'b0;
   end
 
   always_comb begin
-    if (a2 == {ADDRESS_LENGTH{1'b0}})
+    if (a2 != {ADDRESS_LENGTH{1'b0}})
       rd2 = gprs[a2];
     else
       rd2 = 32'b0;