~ruther/verilog-riscv-semestral-project

02405eecab38bfa1d85e88d908b52a589ee53d30 — Rutherther 1 year, 5 months ago 2929a77
fix: force alu operation to addition for storing memory and pc
1 files changed, 6 insertions(+), 1 deletions(-)

M src/control_unit.sv
M src/control_unit.sv => src/control_unit.sv +6 -1
@@ 83,7 83,12 @@ module control_unit(
    .reg_we(reg_we)
  );

  assign alu_op = conditional_jump ? alu_jump_op : alu_reg_op;
  // if jump, set alu_jump_op
  // if loading or storing memory or loading pc, always add
  // else do the register operation
  assign alu_op = conditional_jump ? alu_jump_op :
                  ((load_memory || memory_we || load_pc) ? 3'b000 :
                  alu_reg_op);
  assign alu_add_one = conditional_jump ? alu_jump_add_one : alu_reg_add_one;
  assign alu_negate = conditional_jump ? alu_jump_negate : alu_reg_negate;
  assign alu_signed = conditional_jump ? 0 : alu_reg_signed;

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