~ruther/verilog-riscv-semestral-project

66fd5da9a15539865c07f3516a5e396674a2bf16 — Rutherther 1 year, 5 months ago 2867e24
fix: shift by 5 bits in alu
1 files changed, 2 insertions(+), 2 deletions(-)

M src/alu.sv
M src/alu.sv => src/alu.sv +2 -2
@@ 29,9 29,9 @@ module alu(
      3'b100 : out = a ^ real_b;
      3'b101 : begin
        if (sign)
          out = signed'(a) >>> signed'(real_b);
          out = signed'(a) >>> signed'(real_b[4:0]);
        else
          out = a >> real_b;
          out = a >> real_b[4:0];
      end
      3'b110 : out = a | real_b;
      3'b111 : out = a & real_b;

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