~ruther/verilog-riscv-semestral-project

27fcb8d9421b49a1d1545cb4fb80f9c6f03ebaf8 — Rutherther 1 year, 5 months ago e44bfc9
fix: do not use immediate in alu src for SB
1 files changed, 1 insertions(+), 2 deletions(-)

M src/instruction_decoder.sv
M src/instruction_decoder.sv => src/instruction_decoder.sv +1 -2
@@ 118,8 118,7 @@ module instruction_decoder(
    if (instruction_type == I ||
        instruction_type == U ||
        instruction_type == UJ ||
        instruction_type == S ||
        instruction_type == SB) begin
        instruction_type == S) begin
      use_immediate = 1'b1;
    end
    else begin

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