~ruther/verilog-riscv-semestral-project

300c2dd7 — Rutherther 2 years ago
feat: add program counter
64d33d25 — Rutherther 2 years ago
feat: add program memory
65ab00a4 — Rutherther 2 years ago
chore: ignore obj_dir, vcd outputs
f73ce77d — Rutherther 2 years ago
fix: alu arithmetical shift

Has to have signed as arguments
32ebeea6 — Rutherther 2 years ago
feat(decoder): implement memory mask, conditional jumps
24eccbe0 — Rutherther 2 years ago
refactor: parametrize register file
f8bf441e — Rutherther 2 years ago
chore: move default case
69ced879 — Rutherther 2 years ago
fix: make rd1, rd2 in register_file regs
e3c95ad3 — Rutherther 2 years ago
feat: add instruction decoder
51a684d9 — Rutherther 2 years ago
chore: formatting
8adc02d7 — Rutherther 2 years ago
feat: add basic ram, alu, and register file
9c81ece2 — Rutherther 2 years ago
chore: add gitignore
6780861c — Rutherther 2 years ago
chore: add flake environment