~ruther/verilog-riscv-semestral-project: src 66fd5da9a15539865c07f3516a5e396674a2bf16

~ruther/verilog-riscv-semestral-project

ref: 66fd5da9a15539865c07f3516a5e396674a2bf16 verilog-riscv-semestral-project/src d---------

e3c95ad3 — Rutherther 1 year, 7 months ago

feat: add instruction decoder

51a684d9 — Rutherther 1 year, 7 months ago

chore: formatting

8adc02d7 — Rutherther 1 year, 7 months ago

feat: add basic ram, alu, and register file