~ruther/verilog-riscv-semestral-project

e44bfc9ea42a45f5776158e8e51c025f185b4f56 — Rutherther 1 year, 5 months ago 8f631f5
fix: propagate conditional jump from control_unit
1 files changed, 2 insertions(+), 0 deletions(-)

M src/control_unit.sv
M src/control_unit.sv => src/control_unit.sv +2 -0
@@ 47,6 47,8 @@ module control_unit(
  wire       alu_reg_add_one, alu_reg_negate, alu_reg_signed;
  wire       alu_jump_add_one, alu_jump_negate;

  assign jump_instruction = conditional_jump;

  instruction_decoder decoder(
    .instruction(instruction),


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