~ruther/verilog-riscv-semestral-project

64d33d2582c219e00b6c1f7573501ee713da0967 — Rutherther 1 year, 7 months ago 65ab00a
feat: add program memory
1 files changed, 15 insertions(+), 0 deletions(-)

A src/program_memory.sv
A src/program_memory.sv => src/program_memory.sv +15 -0
@@ 0,0 1,15 @@
module program_memory
(
  input [WIDTH - 1:0] addr,
  output [31:0] instruction
);
  parameter WIDTH = 12;
  parameter MEM_SIZE = 1 << (WIDTH - 2) - 1;

  reg [31:0] imem[0:MEM_SIZE];

  initial $readmemh("memfile.dat", imem);

  assign instruction = imem[addr[WIDTH - 1:2]];

endmodule;

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