~ruther/verilog-riscv-semestral-project

27fcb8d9 — Rutherther 2 years ago
fix: do not use immediate in alu src for SB
e44bfc9e — Rutherther 2 years ago
fix: propagate conditional jump from control_unit
8f631f51 — Rutherther 2 years ago
refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.
938d89a2 — Rutherther 2 years ago
refactor: change program mem to file prog mem
0e23dce5 — Rutherther 2 years ago
fix(register_file): output register if addr not zero
82d9e44f — Rutherther 2 years ago
feat: add cpu top level entity
52b05e5d — Rutherther 2 years ago
feat: add control_unit wrapper over instruction_decoder
b7fa590c — Rutherther 2 years ago
chore: add cpu types for various sources

Better orientation by name instead of
number
300c2dd7 — Rutherther 2 years ago
feat: add program counter
64d33d25 — Rutherther 2 years ago
feat: add program memory
65ab00a4 — Rutherther 2 years ago
chore: ignore obj_dir, vcd outputs
f73ce77d — Rutherther 2 years ago
fix: alu arithmetical shift

Has to have signed as arguments
32ebeea6 — Rutherther 2 years ago
feat(decoder): implement memory mask, conditional jumps
24eccbe0 — Rutherther 2 years ago
refactor: parametrize register file
f8bf441e — Rutherther 2 years ago
chore: move default case
69ced879 — Rutherther 2 years ago
fix: make rd1, rd2 in register_file regs
e3c95ad3 — Rutherther 2 years ago
feat: add instruction decoder
51a684d9 — Rutherther 2 years ago
chore: formatting
8adc02d7 — Rutherther 2 years ago
feat: add basic ram, alu, and register file
9c81ece2 — Rutherther 2 years ago
chore: add gitignore
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