~ruther/verilog-riscv-semestral-project: fix: alu arithmetical shift

~ruther/verilog-riscv-semestral-project

f73ce77d4cbe9181f58b2e1c68b6525b9b67dd68 — Rutherther 1 year, 5 months ago 32ebeea

fix: alu arithmetical shift

Has to have signed as arguments

patch browse .tar.gz

1 files changed, 1 insertions(+), 1 deletions(-)

M src/alu.sv

M src/alu.sv => src/alu.sv +1 -1

@@ 29,7 29,7 @@ module alu(
       3'b100 : out = a ^ real_b;
       3'b101 : begin
         if (sign)
-          out = a >>> real_b;
+          out = signed'(a) >>> signed'(real_b);
         else
           out = a >> real_b;
       end

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