~ruther/verilog-riscv-semestral-project

b7fa590c93b0d8e3e647fb08ecf033e314ece360 — Rutherther 1 year, 5 months ago 300c2dd
chore: add cpu types for various sources

Better orientation by name instead of
number
1 files changed, 6 insertions(+), 0 deletions(-)

A src/cpu_types.sv
A src/cpu_types.sv => src/cpu_types.sv +6 -0
@@ 0,0 1,6 @@
package cpu_types;
  typedef enum bit[0:0] { PC_PLUS, PC_ALU } pc_source_t;
  typedef enum bit[0:0] { REG_FILE_RS1, PC } alu_1_source_t;
  typedef enum bit[0:0] { REG_FILE_RS2, IMMEDIATE } alu_2_source_t;
  typedef enum bit[1:0] { RD_ALU, RD_PC_PLUS, RD_MEMORY } reg_rd_source_t;
endpackage

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