~ruther/verilog-riscv-semestral-project

938d89a274f0e1a4c50cc75857cffaa30e2d6f68 — Rutherther 1 year, 5 months ago 0e23dce
refactor: change program mem to file prog mem
1 files changed, 3 insertions(+), 2 deletions(-)

R src/{program_memory.sv => file_program_memory.sv}
R src/program_memory.sv => src/file_program_memory.sv +3 -2
@@ 1,14 1,15 @@
module program_memory
module file_program_memory
(
  input [WIDTH - 1:0] addr,
  output [31:0] instruction
);
  parameter FILE_NAME = "memfile.dat";
  parameter WIDTH = 12;
  parameter MEM_SIZE = 1 << (WIDTH - 2) - 1;

  reg [31:0] imem[0:MEM_SIZE];

  initial $readmemh("memfile.dat", imem);
  initial $readmemh(FILE_NAME, imem);

  assign instruction = imem[addr[WIDTH - 1:2]];


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