~ruther/verilog-riscv-semestral-project (66fd5da9a15539865c07f3516a5e396674a2bf16): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

66fd5da9 — Rutherther fix: shift by 5 bits in alu 1 year, 7 months ago

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.envrc

10 bytes

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.gitignore

52 bytes

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flake.lock

1.5 KiB

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flake.nix

1.1 KiB

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src/

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testbench/

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