~ruther/verilog-riscv-semestral-project

f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3 — Rutherther 1 year, 7 months ago 69ced87
chore: move default case
1 files changed, 2 insertions(+), 1 deletions(-)

M src/alu.sv
M src/alu.sv => src/alu.sv +2 -1
@@ 20,7 20,7 @@ module alu(


  always_comb begin
    out = {WIDTH{1'bX}};

    case (op)
      3'b000 : out = a + real_b;
      3'b001 : out = a << real_b;


@@ 35,6 35,7 @@ module alu(
      end
      3'b110 : out = a | real_b;
      3'b111 : out = a & real_b;
      default: out = {WIDTH{1'bX}};
    endcase
  end


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