~ruther/verilog-riscv-semestral-project

300c2dd744c0a39f8ca60ce97c3015c7af4c27cf — Rutherther 1 year, 5 months ago 64d33d2
feat: add program counter
1 files changed, 18 insertions(+), 0 deletions(-)

A src/program_counter.sv
A src/program_counter.sv => src/program_counter.sv +18 -0
@@ 0,0 1,18 @@
// + 4 normally
// or if should jump, jump to given address (either pc + imm or rs1 + imm)

module program_counter(
  input                    clk,
  input                    rst_n,
  input [WIDTH - 1:0]      pc_next,
  output reg [WIDTH - 1:0] pc
);
  parameter WIDTH = 12;

  always_ff @ (posedge clk)
    if (rst_n == 1'b0)
      pc <= 0;
    else
      pc <= pc_next;

endmodule

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