~ruther/verilog-riscv-semestral-project: main

f8bf441e — Rutherther 2 years ago

chore: move default case

69ced879 — Rutherther 2 years ago

fix: make rd1, rd2 in register_file regs

e3c95ad3 — Rutherther 2 years ago

feat: add instruction decoder

51a684d9 — Rutherther 2 years ago

chore: formatting

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file

9c81ece2 — Rutherther 2 years ago

chore: add gitignore

6780861c — Rutherther 2 years ago

chore: add flake environment