~ruther/verilog-riscv-semestral-project

2867e24626f7c4643ffa93cb6ea28f24d3eb2dae — Rutherther 1 year, 5 months ago 2f09f76
fix: do not set subtract for non-R instructions
1 files changed, 1 insertions(+), 1 deletions(-)

M src/instruction_decoder.sv
M src/instruction_decoder.sv => src/instruction_decoder.sv +1 -1
@@ 106,7 106,7 @@ module instruction_decoder(
  always_comb begin
    alu_reg_add_one = 1'b0;
    alu_reg_negate = 1'b0;
    if (funct3 == 0 && funct7[5] == 1) begin
    if (instruction_type == R && funct3 == 0 && funct7[5] == 1) begin
      // subtraction
      alu_reg_add_one = 1'b1;
      alu_reg_negate = 1'b1;

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