~ruther/verilog-riscv-semestral-project

ref: c682cc068ee41da1b00fbd51dfb79f9cd5560d0d verilog-riscv-semestral-project/src d---------
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
9f4ac4dc — Rutherther 2 years ago
fix: jump according to zero flag, not LSB zero!!
ca9604e2 — Rutherther 2 years ago
fix: offset ram by bytes, not bits
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
bc02aba5 — Rutherther 2 years ago
fix: make sure alu is zeroed on memory load, write, jump
66fd5da9 — Rutherther 2 years ago
fix: shift by 5 bits in alu
2867e246 — Rutherther 2 years ago
fix: do not set subtract for non-R instructions
2f09f768 — Rutherther 2 years ago
fix: make immediates sign extended
7ad51766 — Rutherther 2 years ago
fix: remove duplicit instruction and pc in cpu
02405eec — Rutherther 2 years ago
fix: force alu operation to addition for storing memory and pc
27fcb8d9 — Rutherther 2 years ago
fix: do not use immediate in alu src for SB
e44bfc9e — Rutherther 2 years ago
fix: propagate conditional jump from control_unit
8f631f51 — Rutherther 2 years ago
refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.
938d89a2 — Rutherther 2 years ago
refactor: change program mem to file prog mem
0e23dce5 — Rutherther 2 years ago
fix(register_file): output register if addr not zero
82d9e44f — Rutherther 2 years ago
feat: add cpu top level entity
52b05e5d — Rutherther 2 years ago
feat: add control_unit wrapper over instruction_decoder
b7fa590c — Rutherther 2 years ago
chore: add cpu types for various sources

Better orientation by name instead of
number
300c2dd7 — Rutherther 2 years ago
feat: add program counter
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