~ruther/verilog-riscv-semestral-project: fix: jump according to zero flag, not LSB zero!!

2 files changed, 3 insertions(+), 3 deletions(-)

M src/cpu.sv
M src/instruction_decoder.sv

M src/cpu.sv => src/cpu.sv +1 -1

@@ 75,7 75,7 @@ module cpu(
   end
 
   // pc source
-  assign jump_taken = jump_instruction && (alu_out[0] ^ jump_negate_zero);
+  assign jump_taken = jump_instruction && (alu_zero ^ jump_negate_zero);
   always_comb begin
     case (pc_src)
       PC_PLUS : begin

M src/instruction_decoder.sv => src/instruction_decoder.sv +2 -2

@@ 152,18 152,18 @@ module instruction_decoder(
       end
       3'b100 : begin // blt
         alu_jump_op = 3'b010;
+        jump_negate_zero = 1'b1;
         // less than 011
       end
       3'b101 : begin // bge
         alu_jump_op = 3'b010;
-        jump_negate_zero = 1'b1;
       end
       3'b110 : begin // bltu
         alu_jump_op = 3'b011;
+        jump_negate_zero = 1'b1;
       end
       3'b111 : begin // bgeu
         alu_jump_op = 3'b011;
-        jump_negate_zero = 1'b1;
       end
       default : ;
     endcase