~ruther/verilog-riscv-semestral-project

9f4ac4dc — Rutherther 2 years ago
fix: jump according to zero flag, not LSB zero!!
adfdc041 — Rutherther 2 years ago
feat: add branches.c test
0a9a14b7 — Rutherther 2 years ago
test: add ram test
057ee98b — Rutherther 2 years ago
chore: add generated bin, obj gitignore files
cc87c7b8 — Rutherther 2 years ago
fix(Makefile): make objdump and all testbenches work
181e94c4 — Rutherther 2 years ago
chore: add risc toolchain to flake
6ce1c838 — Rutherther 2 years ago
chore: remove gcc generated file
ca9604e2 — Rutherther 2 years ago
fix: offset ram by bytes, not bits
30a7f949 — Rutherther 2 years ago
feat: add basic testing programs
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
bc02aba5 — Rutherther 2 years ago
fix: make sure alu is zeroed on memory load, write, jump
66fd5da9 — Rutherther 2 years ago
fix: shift by 5 bits in alu
2867e246 — Rutherther 2 years ago
fix: do not set subtract for non-R instructions
2f09f768 — Rutherther 2 years ago
fix: make immediates sign extended
773f4b99 — Rutherther 2 years ago
test: add simple cpu test
7ad51766 — Rutherther 2 years ago
fix: remove duplicit instruction and pc in cpu
02405eec — Rutherther 2 years ago
fix: force alu operation to addition for storing memory and pc
2929a779 — Rutherther 2 years ago
test: add basic testbenches
27fcb8d9 — Rutherther 2 years ago
fix: do not use immediate in alu src for SB
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