~ruther/verilog-riscv-semestral-project

fix: jump according to zero flag, not LSB zero!!
feat: add branches.c test
test: add ram test
chore: add generated bin, obj gitignore files
fix(Makefile): make objdump and all testbenches work
chore: add risc toolchain to flake
chore: remove gcc generated file
fix: offset ram by bytes, not bits
feat: add basic testing programs
chore: add makefile for both verilog and c
feat: implement sb, sh, lb, lh support via masking
fix: make sure alu is zeroed on memory load, write, jump
fix: shift by 5 bits in alu
fix: do not set subtract for non-R instructions
fix: make immediates sign extended
test: add simple cpu test
fix: remove duplicit instruction and pc in cpu
fix: force alu operation to addition for storing memory and pc
test: add basic testbenches
fix: do not use immediate in alu src for SB
Next
Do not follow this link