2 files changed, 47 insertions(+), 23 deletions(-)

M src/alu.sv
M src/register_file.sv

@@ 2,30 2,43 @@ module alu(
   input [2:0]              op,
   input [WIDTH - 1:0]      a, b,
   input                    sign,
+  input                    b_add_one,
+  input                    b_negate,
   output reg [WIDTH - 1:0] out,
   output reg               zero_flag);
   parameter                WIDTH = 32;
 
+  reg [WIDTH - 1:0]        real_b;
+
+  always_comb begin
+    if (b_negate)
+      real_b = ~b;
+    else
+      real_b = b;
+    real_b = real_b + (b_add_one ? 1 : 0);
+  end
+
+
   always_comb begin
     out = {WIDTH{1'bX}};
     case (op)
-      3'b000 : out = a + b;
-      3'b001 : out = a << b;
-      3'b010 : out = signed'(a) < signed'(b);
-      3'b011 : out = (a < b) ? 1 : 0;
-      3'b100 : out = a ^ b;
+      3'b000 : out = a + real_b;
+      3'b001 : out = a << real_b;
+      3'b010 : out = (signed'(a) < signed'(real_b)) ? 1 : 0;
+      3'b011 : out = (a < real_b) ? 1 : 0;
+      3'b100 : out = a ^ real_b;
       3'b101 : begin
         if (sign)
-          out = a >> b;
+          out = a >>> real_b;
         else
-          out = a >>> b;
-      end // should support arithmetical as well a >>> b
-      3'b110 : out = a | b;
-      3'b111 : out = a & b;
+          out = a >> real_b;
+      end
+      3'b110 : out = a | real_b;
+      3'b111 : out = a & real_b;
     endcase
   end
 
   always_comb
-    zero_flag <= (out == 0) ? 1 : 0;
+    zero_flag = (out == 0) ? 1 : 0;
 
 endmodule

@@ 1,26 1,37 @@
-module register_file(clk, A1, A2, A3, WE3, WD3, RD1, RD2);
+module register_file(clk, a1, a2, a3, we3, wd3, rd1, rd2);
 
   input clk;
-  input [4:0] A1;
-  input [4:0] A2;
-  input [4:0] A3;
+  input [4:0] a1;
+  input [4:0] a2;
+  input [4:0] a3;
 
-  input       WE3; // write enable
-  input [31:0] WD3; // write data
+  input       we3; // write enable
+  input [31:0] wd3; // write data
 
-  output [31:0] RD1;
-  output [31:0] RD2;
+  output [31:0] rd1;
+  output [31:0] rd2;
 
   reg [31:0]    gprs [32];
 
   wire          clk;
 
-  assign RD1 = gprs[A1];
-  assign RD2 = gprs[A2];
+  always_comb begin
+    if (a1 == 5'b0)
+      rd1 = gprs[a1];
+    else
+      rd1 = 32'b0;
+  end
+
+  always_comb begin
+    if (a2 == 5'b0)
+      rd2 = gprs[a2];
+    else
+      rd2 = 32'b0;
+  end
 
   always_ff @(posedge clk) begin
-    if (WE3)
-      gprs[A3] <= WD3;
+    if (we3 && a3 != 5'b0)
+      gprs[a3] <= wd3;
   end
 
 endmodule