3 files changed, 71 insertions(+), 0 deletions(-)

A src/alu.sv
A src/ram.sv
A src/register_file.sv

@@ 0,0 1,31 @@
+module alu(
+  input [2:0]              op,
+  input [WIDTH - 1:0]      a, b,
+  input                    sign,
+  output reg [WIDTH - 1:0] out,
+  output reg               zero_flag);
+  parameter                WIDTH = 32;
+
+  always_comb begin
+    out = {WIDTH{1'bX}};
+    case (op)
+      3'b000 : out = a + b;
+      3'b001 : out = a << b;
+      3'b010 : out = signed'(a) < signed'(b);
+      3'b011 : out = (a < b) ? 1 : 0;
+      3'b100 : out = a ^ b;
+      3'b101 : begin
+        if (sign)
+          out = a >> b;
+        else
+          out = a >>> b;
+      end // should support arithmetical as well a >>> b
+      3'b110 : out = a | b;
+      3'b111 : out = a & b;
+    endcase
+  end
+
+  always_comb
+    zero_flag <= (out == 0) ? 1 : 0;
+
+endmodule

@@ 0,0 1,13 @@
+module ram (
+  input         clk, we,
+  input [31:0]  a, wd,
+  output [31:0] rd);
+
+  reg [31:0]    RAM[0:127];
+
+  assign rd = RAM[a[8:2]]; // word aligned
+
+  always @(posedge clk)
+    if(we) RAM[a[8:2]] <= wd;
+
+endmodule

@@ 0,0 1,27 @@
+module register_file(clk, A1, A2, A3, WE3, WD3, RD1, RD2);
+
+  input clk;
+  input [4:0] A1;
+  input [4:0] A2;
+  input [4:0] A3;
+
+  input       WE3; // write enable
+  input [31:0] WD3; // write data
+
+  output [31:0] RD1;
+  output [31:0] RD2;
+
+  reg [31:0]    gprs [32];
+
+  wire          clk;
+
+  assign RD1 = gprs[A1];
+  assign RD2 = gprs[A2];
+
+  always_ff @(posedge clk) begin
+    if (WE3)
+      gprs[A3] <= WD3;
+  end
+
+endmodule
+//