~ruther/verilog-riscv-semestral-project

adfdc041e204e13c59c32d866fb2ee288b272c57 — Rutherther 1 year, 5 months ago 0a9a14b
feat: add branches.c test
1 files changed, 43 insertions(+), 0 deletions(-)

A programs/branches.c
A programs/branches.c => programs/branches.c +43 -0
@@ 0,0 1,43 @@
void main()
{
    int a = 1;
    int b = 5;
    int c = 0;

    if (a < b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a >= b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a != b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a == b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a <= b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a > b) {
        c = 1;
    } else {
        c = 2;
    }

}

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