~ruther/verilog-riscv-semestral-project

30a7f9492e5e15f2d64dded11bc5080af6b54ec5 — Rutherther 1 year, 5 months ago 707b5bf
feat: add basic testing programs
5 files changed, 93 insertions(+), 0 deletions(-)

A programs/add.c
A programs/add.s
A programs/link.ld
A programs/start.S
A programs/tests.c
A programs/add.c => programs/add.c +11 -0
@@ 0,0 1,11 @@
int add(int a, int b)
{
    return a + b;
}

void main()
{
    int a = 20;
    int b = 30;
    int c = add(a, b);
}

A programs/add.s => programs/add.s +46 -0
@@ 0,0 1,46 @@
	.file	"add.c"
	.option nopic
	.attribute arch, "rv32i2p1"
	.attribute unaligned_access, 0
	.attribute stack_align, 16
	.text
	.align	2
	.globl	add
	.type	add, @function
add:
	addi	sp,sp,-32
	sw	s0,28(sp)
	addi	s0,sp,32
	sw	a0,-20(s0)
	sw	a1,-24(s0)
	lw	a4,-20(s0)
	lw	a5,-24(s0)
	add	a5,a4,a5
	mv	a0,a5
	lw	s0,28(sp)
	addi	sp,sp,32
	jr	ra
	.size	add, .-add
	.align	2
	.globl	main
	.type	main, @function
main:
	addi	sp,sp,-32
	sw	ra,28(sp)
	sw	s0,24(sp)
	addi	s0,sp,32
	li	a5,20
	sw	a5,-20(s0)
	li	a5,30
	sw	a5,-24(s0)
	lw	a1,-24(s0)
	lw	a0,-20(s0)
	call	add
	sw	a0,-28(s0)
	nop
	lw	ra,28(sp)
	lw	s0,24(sp)
	addi	sp,sp,32
	jr	ra
	.size	main, .-main
	.ident	"GCC: (GNU) 12.2.0"

A programs/link.ld => programs/link.ld +21 -0
@@ 0,0 1,21 @@
MEMORY
{
    ram : ORIGIN = 0x00000000, LENGTH = 1K - 1
}

SECTIONS
{
	.text = 0x0;
    .bss : {
        __bss_start = .;
        *(.bss)
        *(COMMON)
        __bss_end = .;
    } > ram
    .stack : {
        __stack_start = .;
        *(.stack)
        __stack_end = .;
    } > ram
}


A programs/start.S => programs/start.S +8 -0
@@ 0,0 1,8 @@
.global _start

.text
_start:
    addi sp, x0, 127
    call main
_loop:
    j _loop

A programs/tests.c => programs/tests.c +7 -0
@@ 0,0 1,7 @@
void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}

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