fix(Makefile): make objdump and all testbenches work

chore: add risc toolchain to flake

chore: remove gcc generated file

fix: offset ram by bytes, not bits

feat: add basic testing programs

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

fix: make sure alu is zeroed on memory load, write, jump

fix: shift by 5 bits in alu

fix: do not set subtract for non-R instructions

fix: make immediates sign extended

test: add simple cpu test

fix: remove duplicit instruction and pc in cpu

fix: force alu operation to addition for storing memory and pc

test: add basic testbenches

fix: do not use immediate in alu src for SB

fix: propagate conditional jump from control_unit

refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.

refactor: change program mem to file prog mem

fix(register_file): output register if addr not zero