~ruther/verilog-riscv-semestral-project

057ee98bbecfb8a284b67bef50b04b70ae18e220 — Rutherther 1 year, 5 months ago cc87c7b
chore: add generated bin, obj gitignore files
1 files changed, 6 insertions(+), 0 deletions(-)

M .gitignore
M .gitignore => .gitignore +6 -0
@@ 6,3 6,9 @@ tmp/
.direnv/
obj_dir/
*.vcd

waves/
programs/bin/
*.o
*.bin
*.dat

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