~ruther/verilog-riscv-semestral-project

cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c — Rutherther 1 year, 5 months ago 181e94c
fix(Makefile): make objdump and all testbenches work
1 files changed, 2 insertions(+), 2 deletions(-)

M Makefile
M Makefile => Makefile +2 -2
@@ 21,7 21,7 @@ show: ./waves/$(MODULE).vcd
./waves:
	mkdir -p $@

./obj_dir/Vtb_%: testbench/tb_%.sv src/%.sv
./obj_dir/Vtb_%: testbench/tb_%.sv src/*.sv
	verilator --binary --trace \
		src/cpu_types.sv \
		src/instruction_decoder.sv \


@@ 64,7 64,7 @@ OBJCOPY=riscv32-none-elf-objcopy
./programs/bin/%.dat: ./programs/bin/%.bin
	od $< -t x4 -A n > $@

objdump/%: ./programs/bin/%.bin
objdump/%: ./programs/bin/start-%.o
	$(OBJDUMP) -d -M no-aliases $<

.PHONY: clean

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