5 files changed, 79 insertions(+), 4 deletions(-)

A Makefile
M testbench/tb_alu.sv
M testbench/tb_control_unit.sv
M testbench/tb_cpu_simple.sv
M testbench/tb_register_file.sv

@@ 0,0 1,75 @@
+MODULE=tb_control_unit
+
+## Verilog part
+.PHONY:sim
+sim: waveform.vcd
+
+.PHONY:verilate
+verilate: .stamp.verilate
+
+.PHONY:build
+
+build: obj_dir/V$(MODULE)
+
+.PHONY:waves
+show: ./waves/$(MODULE).vcd
+	gtkwave ./waves/$(MODULE).vcd
+
+./waves/%.vcd: ./obj_dir/V% ./waves
+	$<
+
+./waves:
+	mkdir -p $@
+
+./obj_dir/Vtb_%: testbench/tb_%.sv src/%.sv
+	verilator --binary --trace \
+		src/cpu_types.sv \
+		src/instruction_decoder.sv \
+		src/control_unit.sv \
+		src/alu.sv \
+		src/register_file.sv \
+		src/program_counter.sv \
+		src/ram.sv \
+		src/cpu.sv \
+		src/file_program_memory.sv \
+		$< \
+        --top $(notdir $(basename $<))
+
+## C part
+CFLAGS=-march=rv32i -mabi=ilp32 -O0 -c
+ASFLAGS=-march=rv32i -mabi=ilp32
+LDFLAGS=-Tprograms/link.ld
+
+CC=riscv32-none-elf-gcc
+AS=riscv32-none-elf-as
+LD=riscv32-none-elf-ld
+OBJDUMP=riscv32-none-elf-objdump
+OBJCOPY=riscv32-none-elf-objcopy
+
+./programs/bin:
+	mkdir -p $@
+
+./programs/bin/start.o: ./programs/start.S ./programs/bin
+	$(AS) $(ASFLAGS) $< -o $@
+
+./programs/bin/%.o: ./programs/%.c ./programs/bin
+	$(CC) $(CFLAGS) $< -o $@
+
+./programs/bin/start-%.o: ./programs/bin/start.o ./programs/bin/%.o
+	$(LD) $(LDFLAGS) $^ -o $@
+
+./programs/bin/%.bin: ./programs/bin/start-%.o
+	$(OBJCOPY) $< -O binary $@
+
+./programs/bin/%.dat: ./programs/bin/%.bin
+	od $< -t x4 -A n > $@
+
+objdump/%: ./programs/bin/%.bin
+	$(OBJDUMP) -d -M no-aliases $<
+
+.PHONY: clean
+clean:
+	rm -rf ./waves
+	rm -rf ./programs/bin
+	rm -rf ./obj_dir
+	rm -rf waveform.vcd

@@ 19,7 19,7 @@ module tb_alu();
   );
 
   initial begin
-    $dumpfile("alu_tb.vcd");
+    $dumpfile("waves/tb_alu.vcd");
     $dumpvars;
 
     a = 30;

@@ 53,7 53,7 @@ module tb_control_unit();
   );
 
   initial begin
-    $dumpfile("control_unit.vcd");
+    $dumpfile("waves/tb_control_unit.vcd");
     $dumpvars;
 
     // addi

@@ 87,7 87,7 @@ module tb_cpu_simple();
   end
 
   initial begin
-    $dumpfile("cpu_simple.vcd");
+    $dumpfile("waves/tb_cpu_simple.vcd");
     $dumpvars;
 
     rst_n = 0;

@@ 25,7 25,7 @@ module tb_register_file();
   end
 
   initial begin
-    $dumpfile("register_file.vcd");
+    $dumpfile("waves/tb_register_file.vcd");
     $dumpvars;
     a1 = 0;
     a2 = 0;