~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/src d---------
chore: remove first unused register
feat: add support for loading and saving ram from disk
feat: pass program to execute by parameter
feat: implement ebreak

Breaks the processor, can
exit the testcase
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
fix: jump according to zero flag, not LSB zero!!
fix: offset ram by bytes, not bits
feat: implement sb, sh, lb, lh support via masking
fix: make sure alu is zeroed on memory load, write, jump
fix: shift by 5 bits in alu
fix: do not set subtract for non-R instructions
fix: make immediates sign extended
fix: remove duplicit instruction and pc in cpu
fix: force alu operation to addition for storing memory and pc
fix: do not use immediate in alu src for SB
fix: propagate conditional jump from control_unit
refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.
refactor: change program mem to file prog mem
fix(register_file): output register if addr not zero
feat: add cpu top level entity
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