~ruther/verilog-riscv-semestral-project: chore: remove first unused register

37437a002b69c937712b58ce3782f510248fcdcc — Rutherther 1 year, 5 months ago 732301c

chore: remove first unused register

patch browse .tar.gz

1 files changed, 1 insertions(+), 1 deletions(-)

M src/register_file.sv

M src/register_file.sv => src/register_file.sv +1 -1

@@ 14,7 14,7 @@ module register_file(clk, a1, a2, a3, we3, wd3, rd1, rd2);
   output reg [WIDTH - 1:0] rd1;
   output reg [WIDTH - 1:0] rd2;
 
-  reg [WIDTH - 1:0]    gprs [SIZE];
+  reg [WIDTH - 1:0]    gprs [1:SIZE-1];
 
   wire          clk;