~ruther/verilog-riscv-semestral-project

ee0204c8aee094b0d30256a61ba9400adb01dd5a — Rutherther 1 year, 5 months ago 11422de 
feat: pass program to execute by parameter
patch browse .tar.gz 
6 files changed, 31 insertions(+), 191 deletions(-)

M Makefile
M src/file_program_memory.sv
D testbench/tb_cpu_branches.sv
D testbench/tb_cpu_gcd.sv
R testbench/{tb_cpu_add.sv => tb_cpu_program.sv}
D testbench/tb_cpu_tests.sv

M Makefile => Makefile +24 -0
@@ 15,12 15,36 @@ build: obj_dir/V$(MODULE)
show: ./waves/$(MODULE).vcd
	gtkwave ./waves/$(MODULE).vcd

./waves/cpu_program_%.vcd: ./obj_dir/Vtb_cpu_program_% ./waves
	$<

./waves/%.vcd: ./obj_dir/V% ./waves
	$<

./waves:
	mkdir -p $@

# These are runtime dependencies, not build time dependencies.
.PRECIOUS: ./programs/bin/%.dat ./programs/bin/%.bin

./obj_dir/Vtb_cpu_program_%: ./programs/bin/%.dat testbench/tb_cpu_program.sv src/*.sv
	verilator --binary --trace \
		-GCPU_PROGRAM_PATH="\"$<\"" \
		-GCPU_PROGRAM_NAME="\"$(notdir $(basename $<))\"" \
		--trace-max-array 512 \
		src/cpu_types.sv \
		src/instruction_decoder.sv \
		src/control_unit.sv \
		src/alu.sv \
		src/register_file.sv \
		src/program_counter.sv \
		src/ram.sv \
		src/cpu.sv \
		src/file_program_memory.sv \
		testbench/tb_cpu_program.sv \
		-o Vtb_cpu_program_$(notdir $(basename $<)) \
		--top tb_cpu_program

./obj_dir/Vtb_%: testbench/tb_%.sv src/*.sv
	verilator --binary --trace \
		--trace-max-array 512 \


M src/file_program_memory.sv => src/file_program_memory.sv +1 -1
@@ 3,7 3,7 @@ module file_program_memory
  input [WIDTH - 1:0] addr,
  output [31:0] instruction
);
  parameter FILE_NAME = "memfile.dat";
  parameter string FILE_NAME;
  parameter WIDTH = 12;
  parameter MEM_SIZE = 1 << (WIDTH - 2) - 1;



D testbench/tb_cpu_branches.sv => testbench/tb_cpu_branches.sv +0 -62
@@ 1,62 0,0 @@
import cpu_types::*;

module tb_cpu_branches();
  reg clk, rst_n;

  wire [31:0] memory_address, memory_write, memory_out;
  wire [3:0]  memory_write_byte_enable;
  wire        memory_we;

  wire [31:0] pc;
  reg [31:0]  instruction;

  wire        ebreak;

  cpu uut(
    .clk(clk),
    .rst_n(rst_n),

    .instruction(instruction),
    .pc(pc),

    .memory_address(memory_address),
    .memory_out(memory_out),
    .memory_write(memory_write),
    .memory_byte_enable(memory_write_byte_enable),
    .memory_we(memory_we),

    .ebreak(ebreak)
  );

  ram memory_inst(
    .clk(clk),
    .a(memory_address),
    .write_byte_enable(memory_write_byte_enable),
    .we(memory_we),
    .wd(memory_write),
    .rd(memory_out)
  );

  file_program_memory #(.FILE_NAME("programs/bin/branches.dat")) prog_mem_inst(
    .addr(pc[11:0]),
    .instruction(instruction)
  );

  always_ff @ (posedge ebreak) begin
    #15 $finish;
  end

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $dumpfile("waves/tb_cpu_branches.vcd");
    $dumpvars;

    rst_n = 0;
    #20
    rst_n = 1;
  end
endmodule


D testbench/tb_cpu_gcd.sv => testbench/tb_cpu_gcd.sv +0 -62
@@ 1,62 0,0 @@
import cpu_types::*;

module tb_cpu_gcd();
  reg clk, rst_n;

  wire [31:0] memory_address, memory_write, memory_out;
  wire [3:0]  memory_write_byte_enable;
  wire        memory_we;

  wire [31:0] pc;
  reg [31:0]  instruction;

  wire        ebreak;

  cpu uut(
    .clk(clk),
    .rst_n(rst_n),

    .instruction(instruction),
    .pc(pc),

    .memory_address(memory_address),
    .memory_out(memory_out),
    .memory_write(memory_write),
    .memory_byte_enable(memory_write_byte_enable),
    .memory_we(memory_we),

    .ebreak(ebreak)
  );

  ram memory_inst(
    .clk(clk),
    .a(memory_address),
    .write_byte_enable(memory_write_byte_enable),
    .we(memory_we),
    .wd(memory_write),
    .rd(memory_out)
  );

  file_program_memory #(.FILE_NAME("programs/bin/gcd.dat")) prog_mem_inst(
    .addr(pc[11:0]),
    .instruction(instruction)
  );

  always_ff @ (posedge ebreak) begin
    #15 $finish;
  end

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $dumpfile("waves/tb_cpu_gcd.vcd");
    $dumpvars;

    rst_n = 0;
    #20
    rst_n = 1;
  end
endmodule


R testbench/tb_cpu_add.sv => testbench/tb_cpu_program.sv +6 -4
@@ 1,7 1,6 @@

import cpu_types::*;

module tb_cpu_add();
module tb_cpu_program();
  reg clk, rst_n;

  wire [31:0] memory_address, memory_write, memory_out;


@@ 13,6 12,9 @@ module tb_cpu_add();

  wire        ebreak;

  parameter string  CPU_PROGRAM_PATH;
  parameter string  CPU_PROGRAM_NAME;

  cpu uut(
    .clk(clk),
    .rst_n(rst_n),


@@ 38,7 40,7 @@ module tb_cpu_add();
    .rd(memory_out)
  );

  file_program_memory #(.FILE_NAME("programs/bin/add.dat")) prog_mem_inst(
  file_program_memory #(.FILE_NAME(CPU_PROGRAM_PATH)) prog_mem_inst(
    .addr(pc[11:0]),
    .instruction(instruction)
  );


@@ 53,7 55,7 @@ module tb_cpu_add();
  end

  initial begin
    $dumpfile("waves/tb_cpu_add.vcd");
    $dumpfile({"waves/cpu_program_", CPU_PROGRAM_NAME, ".vcd"});
    $dumpvars;

    rst_n = 0;


D testbench/tb_cpu_tests.sv => testbench/tb_cpu_tests.sv +0 -62
@@ 1,62 0,0 @@
import cpu_types::*;

module tb_cpu_tests();
  reg clk, rst_n;

  wire [31:0] memory_address, memory_write, memory_out;
  wire [3:0]  memory_write_byte_enable;
  wire        memory_we;

  wire [31:0] pc;
  reg [31:0]  instruction;

  wire        ebreak;

  cpu uut(
    .clk(clk),
    .rst_n(rst_n),

    .instruction(instruction),
    .pc(pc),

    .memory_address(memory_address),
    .memory_out(memory_out),
    .memory_write(memory_write),
    .memory_byte_enable(memory_write_byte_enable),
    .memory_we(memory_we),

    .ebreak(ebreak)
  );

  ram memory_inst(
    .clk(clk),
    .a(memory_address),
    .write_byte_enable(memory_write_byte_enable),
    .we(memory_we),
    .wd(memory_write),
    .rd(memory_out)
  );

  file_program_memory #(.FILE_NAME("programs/bin/tests.dat")) prog_mem_inst(
    .addr(pc[11:0]),
    .instruction(instruction)
  );

  always_ff @ (posedge ebreak) begin
    #15 $finish;
  end

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $dumpfile("waves/tb_cpu_tests.vcd");
    $dumpvars;

    rst_n = 0;
    #20
    rst_n = 1;
  end
endmodule
Do not follow this link