fix: temporarily turn off switching fetch valid

The instruction is always valid, since
for now jumps are calculated right away,
not one cycle after decode. That means
that next instruction is not fetched!

This is fine for simulation,
but when synthesized I think this
would slow down the processor as there
has to be the register file read performed
along with alu operation in one cycle.

First this should be changed, then uncomment
this line, to make the fetched pc+4 instruction
invalid when jumping.

Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline

docs: better document the stage code, organize it better

chore: import cpu types in stages

chore: recover singlecycle version

feat: add forwarding signal for better debugging

feat: implement pipeline

fix: use reg for procedural assignments

chore: extend memory

tests: add register dump, printing

fix: shift left only by 5 bits

fix: lui, force rs1 zero, always add

feat: add support for official tests

chore: remove first unused register

feat: add support for loading and saving ram from disk

feat: pass program to execute by parameter

feat: implement ebreak

Breaks the processor, can
exit the testcase

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

fix: jump according to zero flag, not LSB zero!!

fix: offset ram by bytes, not bits