~ruther/verilog-riscv-semestral-project: chore: import cpu types in stages

3 files changed, 7 insertions(+), 0 deletions(-)

M src/stages/execute.sv
M src/stages/memory_access.sv
M src/stages/writeback.sv

M src/stages/execute.sv => src/stages/execute.sv +2 -0

@@ 1,3 1,5 @@
+import cpu_types::*;
+
 module execute(
   input clk,

M src/stages/memory_access.sv => src/stages/memory_access.sv +2 -0

@@ 1,3 1,5 @@
+import cpu_types::*;
+
 module memory_access(
   input         clk,

M src/stages/writeback.sv => src/stages/writeback.sv +3 -0

@@ 1,4 1,7 @@
+import cpu_types::*;
+
 module writeback(
+
   input         clk,
 
   output [4:0]  reg_a_write,