~ruther/verilog-riscv-semestral-project

feat: implement pipeline
fix: linker file issues, naming of linked file
fix: use reg for procedural assignments
docs: add basic documentation
chore: update environment description
chore: pass PROGRAM argument to objdump make target
tests: fix ram and control_unit tests to match newest architecture
fix: make Makefile work with memory load, write files
chore: update nixpkgs
tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak
tests: add more custom tests
chore: extend memory
chore: pass in full trace file instead of program name
tests: add register dump, printing
fix: shift left only by 5 bits
fix: lui, force rs1 zero, always add
tests: compile only once, copy proram, memory files to correct locations
chore: add python cache to gitignore
feat: add support for official tests
chore: add python to flake
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