~ruther/verilog-riscv-semestral-project

aeab403896e168bc0c44a65883d46bb96689b7fb — Rutherther 1 year, 4 months ago a6f4c7f
feat: add forwarding signal for better debugging
2 files changed, 7 insertions(+), 0 deletions(-)

M src/forwarder.sv
M src/stages/decode.sv
M src/forwarder.sv => src/forwarder.sv +5 -0
@@ 6,6 6,7 @@ module forwarder(
  input [31:0]      register_file_data,
  input             forwarding_data_status_t data_in_pipeline,

  output            forwarding,
  output reg        stall,
  output reg [31:0] data
);


@@ 17,18 18,22 @@ module forwarder(
  always_comb begin
    stall = 0;
    data = register_file_data;
    forwarding = 0;

    if (read_address != 0 && data_in_pipeline.execute_out.address == read_address) begin
      stall = !data_in_pipeline.execute_out.valid;
      data = data_in_pipeline.execute_out.data;
      forwarding = 1;
    end
    else if (read_address != 0 && data_in_pipeline.access_out.address == read_address) begin
      stall = !data_in_pipeline.access_out.valid;
      data = data_in_pipeline.access_out.data;
      forwarding = 1;
    end
    else if (read_address != 0 && data_in_pipeline.writeback_in.address == read_address) begin
      stall = !data_in_pipeline.writeback_in.valid;
      data = data_in_pipeline.writeback_in.data;
      forwarding = 1;
    end
  end
endmodule

M src/stages/decode.sv => src/stages/decode.sv +2 -0
@@ 96,6 96,7 @@ module decode(
    .register_file_data(reg_rd1),
    .data_in_pipeline(data_in_pipeline),
    .stall(stall_1),
    .forwarding(),
    .data(forwarded_reg_rd1)
  );



@@ 105,6 106,7 @@ module decode(
    .register_file_data(reg_rd2),
    .data_in_pipeline(data_in_pipeline),
    .stall(stall_2),
    .forwarding(),
    .data(forwarded_reg_rd2)
  );


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