2 files changed, 11 insertions(+), 5 deletions(-)

M src/control_unit.sv
M src/instruction_decoder.sv

@@ 41,6 41,7 @@ module control_unit(
 );
 
   wire use_immediate;
+  wire load_immediate;
   wire load_memory;
   wire load_pc, store_pc;
   wire conditional_jump, unconditional_jump;


@@ 83,6 84,7 @@ module control_unit(
 
     .immediate(immediate),
     .use_immediate(use_immediate),
+    .load_immediate(load_immediate),
 
     .reg_rs1(reg_rs1),
     .reg_rs2(reg_rs2),


@@ 92,7 94,7 @@ module control_unit(
 
   // in these cases, alu is used just for addition, nothing else,
   // so use neither alu_jump, neither alu_reg, use zeros
-  assign alu_override = load_memory || memory_we || load_pc || unconditional_jump;
+  assign alu_override = load_memory || memory_we || load_pc || unconditional_jump || load_immediate;
 
   assign alu_op = conditional_jump ? alu_jump_op :
                   alu_override     ? 3'b000      :

@@ 41,6 41,7 @@ module instruction_decoder(
   // whether to use immediate instead of rs2.
   // if false, immediate still may be added to second operand
   output           use_immediate,
+  output           load_immediate,
   output [31:0]    immediate,
 
   // inputs to register file


@@ 62,10 63,6 @@ module instruction_decoder(
   assign funct7 = instruction[31:25];
   assign opcode = instruction[6:0];
 
-  assign reg_rs1 = instruction[19:15];
-  assign reg_rs2 = instruction[24:20];
-  assign reg_rd = instruction[11:7];
-
   // load memory mask/size
   always_comb begin
     memory_mask = MEM_WORD;


@@ 201,8 198,13 @@ module instruction_decoder(
     reg_we = 1'b1;
     conditional_jump = 1'b0;
     unconditional_jump = 1'b0;
+    load_immediate = 1'b0;
     ebreak = 1'b0;
 
+    reg_rs1 = instruction[19:15];
+    reg_rs2 = instruction[24:20];
+    reg_rd = instruction[11:7];
+
     // TODO: multiplication
     // NOTE: ecall, ebreak, CSRRW, CSRRS, SCRRC, CSRRWI, CSRRSI, CSRRCI unsupported
     case (opcode[6:2])


@@ 230,6 232,8 @@ module instruction_decoder(
       end
       5'b01101 : begin // load upper imm
         reg_we = 1'b1;
+        load_immediate = 1'b1;
+        reg_rs1 = 5'b0;
       end
       5'b00101 : begin // add upper imm to PC
         load_pc = 1'b1;