~ruther/verilog-riscv-semestral-project

aeab4038 — Rutherther 2 years ago
feat: add forwarding signal for better debugging
a6f4c7fc — Rutherther 2 years ago
chore: add new files to compilation list
89310129 — Rutherther 2 years ago
feat: implement pipeline
d4e70aa6 — Rutherther 2 years ago
fix: linker file issues, naming of linked file
c5e322db — Rutherther 2 years ago
fix: use reg for procedural assignments
b0f87028 — Rutherther 2 years ago
docs: add basic documentation
60517957 — Rutherther 2 years ago
chore: update environment description
94c41794 — Rutherther 2 years ago
chore: pass PROGRAM argument to objdump make target
db85fb35 — Rutherther 2 years ago
tests: fix ram and control_unit tests to match newest architecture
280332ea — Rutherther 2 years ago
fix: make Makefile work with memory load, write files
06261583 — Rutherther 2 years ago
chore: update nixpkgs
73cf8a16 — Rutherther 2 years ago
tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak
a079c57b — Rutherther 2 years ago
tests: add more custom tests
df876b38 — Rutherther 2 years ago
chore: extend memory
7d544e62 — Rutherther 2 years ago
chore: pass in full trace file instead of program name
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
38e84297 — Rutherther 2 years ago
fix: shift left only by 5 bits
740085c8 — Rutherther 2 years ago
fix: lui, force rs1 zero, always add
18eeb2c5 — Rutherther 2 years ago
tests: compile only once, copy proram, memory files to correct locations
1d7c9233 — Rutherther 2 years ago
chore: add python cache to gitignore
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