~ruther/verilog-riscv-semestral-project: fix: temporarily turn off switching fetch valid

7581533cf757a3434d732348b90205ff6be3b404 — Rutherther 1 year, 3 months ago f8e4e3e

fix: temporarily turn off switching fetch valid

The instruction is always valid, since
for now jumps are calculated right away,
not one cycle after decode. That means
that next instruction is not fetched!

This is fine for simulation,
but when synthesized I think this
would slow down the processor as there
has to be the register file read performed
along with alu operation in one cycle.

First this should be changed, then uncomment
this line, to make the fetched pc+4 instruction
invalid when jumping.

patch browse .tar.gz

1 files changed, 1 insertions(+), 1 deletions(-)

M src/stages/fetch.sv

M src/stages/fetch.sv => src/stages/fetch.sv +1 -1

@@ 11,6 11,6 @@ module fetch(
   assign stage_out.instruction.instruction = mem_instruction;
   assign stage_out.pc = pc;
 
-  assign stage_out.valid = !jump;
+  assign stage_out.valid = 1; // !jump; -- TODO make jumps one cycle after
   assign stage_out.ready = 1;
 endmodule