~ruther/verilog-riscv-semestral-project

df876b38b787b7f1e9120775311a0b1a17e2758b — Rutherther 1 year, 5 months ago 7d544e6
chore: extend memory
1 files changed, 3 insertions(+), 3 deletions(-)

M src/ram.sv
M src/ram.sv => src/ram.sv +3 -3
@@ 8,9 8,9 @@ module ram (
  output [31:0] rd);

  reg [31:0]      mask;
  reg [31:0]      memory[1023];
  reg [31:0]      memory[8092];

  assign rd = memory[a[11:2]]; // word aligned
  assign rd = memory[a[14:2]]; // word aligned

  parameter        LOAD_FILE = 0;
  parameter string LOAD_FILE_PATH = "";


@@ 43,6 43,6 @@ module ram (

  always_ff @ (posedge clk)
    if(we)
      memory[a[11:2]] = (rd & ~mask) | (wd & mask);
      memory[a[14:2]] = (rd & ~mask) | (wd & mask);

endmodule

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