~ruther/verilog-riscv-semestral-project

38e84297e0e6abf0ec14d91878d5210792b801bd — Rutherther 1 year, 5 months ago 740085c
fix: shift left only by 5 bits
1 files changed, 1 insertions(+), 1 deletions(-)

M src/alu.sv
M src/alu.sv => src/alu.sv +1 -1
@@ 23,7 23,7 @@ module alu(

    case (op)
      3'b000 : out = a + real_b;
      3'b001 : out = a << real_b;
      3'b001 : out = a << real_b[4:0];
      3'b010 : out = (signed'(a) < signed'(real_b)) ? 1 : 0;
      3'b011 : out = (a < real_b) ? 1 : 0;
      3'b100 : out = a ^ real_b;

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