~ruther/verilog-riscv-semestral-project

chore: move inital sp to 1020
feat: add support for loading and saving ram from disk
feat: pass program to execute by parameter
11422de0 — Rutherther 2 years ago
feat: store c results in memory addr 0
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
5fe03098 — Rutherther 2 years ago
chore: trace memory array
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
e7b5d989 — Rutherther 2 years ago
test: add cpu testbenches for c programs
bb32d2dd — Rutherther 2 years ago
feat: add gcd program for testing
9f4ac4dc — Rutherther 2 years ago
fix: jump according to zero flag, not LSB zero!!
adfdc041 — Rutherther 2 years ago
feat: add branches.c test
0a9a14b7 — Rutherther 2 years ago
test: add ram test
057ee98b — Rutherther 2 years ago
chore: add generated bin, obj gitignore files
cc87c7b8 — Rutherther 2 years ago
fix(Makefile): make objdump and all testbenches work
181e94c4 — Rutherther 2 years ago
chore: add risc toolchain to flake
6ce1c838 — Rutherther 2 years ago
chore: remove gcc generated file
ca9604e2 — Rutherther 2 years ago
fix: offset ram by bytes, not bits
30a7f949 — Rutherther 2 years ago
feat: add basic testing programs
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
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