~ruther/verilog-riscv-semestral-project

5fe030988a21d47dd13af35a9b8697b2181cb6b7 — Rutherther 1 year, 5 months ago a400ace
chore: trace memory array
1 files changed, 1 insertions(+), 0 deletions(-)

M Makefile
M Makefile => Makefile +1 -0
@@ 23,6 23,7 @@ show: ./waves/$(MODULE).vcd

./obj_dir/Vtb_%: testbench/tb_%.sv src/*.sv
	verilator --binary --trace \
		--trace-max-array 512 \
		src/cpu_types.sv \
		src/instruction_decoder.sv \
		src/control_unit.sv \

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