~ruther/verilog-riscv-semestral-project

a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 — Rutherther 1 year, 4 months ago 8931012
chore: add new files to compilation list
1 files changed, 10 insertions(+), 0 deletions(-)

M tests/comp_list.lst
M tests/comp_list.lst => tests/comp_list.lst +10 -0
@@ 4,6 4,16 @@ src/control_unit.sv
src/alu.sv
src/register_file.sv
src/program_counter.sv

src/forwarder.sv
src/jumps.sv

src/stages/fetch.sv
src/stages/decode.sv
src/stages/execute.sv
src/stages/memory_access.sv
src/stages/writeback.sv

src/ram.sv
src/cpu.sv
src/file_program_memory.sv

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