~ruther/verilog-riscv-semestral-project

docs: add basic documentation
chore: update environment description
chore: pass PROGRAM argument to objdump make target
tests: fix ram and control_unit tests to match newest architecture
fix: make Makefile work with memory load, write files
chore: update nixpkgs
tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak
a079c57b — Rutherther 2 years ago
tests: add more custom tests
df876b38 — Rutherther 2 years ago
chore: extend memory
7d544e62 — Rutherther 2 years ago
chore: pass in full trace file instead of program name
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
38e84297 — Rutherther 2 years ago
fix: shift left only by 5 bits
740085c8 — Rutherther 2 years ago
fix: lui, force rs1 zero, always add
18eeb2c5 — Rutherther 2 years ago
tests: compile only once, copy proram, memory files to correct locations
1d7c9233 — Rutherther 2 years ago
chore: add python cache to gitignore
51842d38 — Rutherther 2 years ago
feat: add support for official tests
7f5ffd17 — Rutherther 2 years ago
chore: add python to flake
34b74f06 — Rutherther 2 years ago
tests: add python test environment for custom tests
bde9255c — Rutherther 2 years ago
chore: load gcd parameters from memory
37437a00 — Rutherther 2 years ago
chore: remove first unused register
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