~ruther/verilog-riscv-semestral-project: tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak

73cf8a16605792f3455e04745c5e0007e1f08be5 — Rutherther 1 year, 4 months ago a079c57

tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak

patch browse .tar.gz

1 files changed, 4 insertions(+), 3 deletions(-)

M testbench/tb_cpu_simple.sv

M testbench/tb_cpu_simple.sv => testbench/tb_cpu_simple.sv +4 -3

@@ 35,11 35,12 @@ module tb_cpu_simple();
     .write_byte_enable(memory_write_byte_enable),
     .we(memory_we),
     .wd(memory_write),
-    .rd(memory_out)
+    .rd(memory_out),
+    .dump(0)
   );
 
-  always_ff @ (posedge ebreak) begin
-    #15 $finish;
+  initial begin
+    #200 $finish;
   end
 
   always_comb begin