~ruther/verilog-riscv-semestral-project: chore: pass in full trace file instead of program name

7d544e62c57a7e944d1572d147f7b271333a75aa — Rutherther 1 year, 5 months ago 308a146

chore: pass in full trace file instead of program name

patch browse .tar.gz

1 files changed, 1 insertions(+), 1 deletions(-)

M Makefile

M Makefile => Makefile +1 -1

@@ 30,7 30,7 @@ show: ./waves/$(MODULE).vcd
 ./obj_dir/Vtb_cpu_program_%: ./programs/bin/%.dat testbench/tb_cpu_program.sv src/*.sv
 	verilator --binary --trace \
 		-GCPU_PROGRAM_PATH="\"$<\"" \
-		-GCPU_PROGRAM_NAME="\"$(notdir $(basename $<))\"" \
+		-GTRACE_FILE_PATH="\"waves/cpu_program_$(notdir $(basename $<)).vcd\"" \
 		--trace-max-array 512 \
 		src/cpu_types.sv \
 		src/instruction_decoder.sv \