~ruther/verilog-riscv-semestral-project

tests: add more custom tests
chore: extend memory
chore: pass in full trace file instead of program name
tests: add register dump, printing
fix: shift left only by 5 bits
fix: lui, force rs1 zero, always add
tests: compile only once, copy proram, memory files to correct locations
chore: add python cache to gitignore
feat: add support for official tests
chore: add python to flake
tests: add python test environment for custom tests
chore: load gcd parameters from memory
chore: remove first unused register
chore: move inital sp to 1020
feat: add support for loading and saving ram from disk
feat: pass program to execute by parameter
feat: store c results in memory addr 0
feat: implement ebreak

Breaks the processor, can
exit the testcase
chore: trace memory array
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
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