~ruther/verilog-riscv-semestral-project

ref: 82d9e44f3229f6554dade8f51988d313a1df02dc verilog-riscv-semestral-project/src d---------
feat: add cpu top level entity
feat: add control_unit wrapper over instruction_decoder
chore: add cpu types for various sources

Better orientation by name instead of
number
feat: add program counter
feat: add program memory
fix: alu arithmetical shift

Has to have signed as arguments
feat(decoder): implement memory mask, conditional jumps
refactor: parametrize register file
chore: move default case
fix: make rd1, rd2 in register_file regs
feat: add instruction decoder
chore: formatting
feat: add basic ram, alu, and register file
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