fix: temporarily turn off switching fetch valid

The instruction is always valid, since
for now jumps are calculated right away,
not one cycle after decode. That means
that next instruction is not fetched!

This is fine for simulation,
but when synthesized I think this
would slow down the processor as there
has to be the register file read performed
along with alu operation in one cycle.

First this should be changed, then uncomment
this line, to make the fetched pc+4 instruction
invalid when jumping.

Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline

docs: better document the stage code, organize it better

docs: document pipeline a bit

chore: import cpu types in stages

chore: recover singlecycle version

feat: add forwarding signal for better debugging

chore: add new files to compilation list

feat: implement pipeline

fix: linker file issues, naming of linked file

fix: use reg for procedural assignments

docs: add basic documentation

chore: update environment description

chore: pass PROGRAM argument to objdump make target

tests: fix ram and control_unit tests to match newest architecture

fix: make Makefile work with memory load, write files

chore: update nixpkgs

tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak

tests: add more custom tests

chore: extend memory